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| ASAHI KASEI [AK4368EG] AK4368EG DAC with built-in PLL & HP-AMP GENERAL DESCRIPTION The AK4368 is 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is synchronized to typical mobile phone clock frequencies. The AK4368 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The AK4368 includes a 3-D stereo enhancement circuit that operates with both the headphone amplifier and the stereo lineout. The integrated headphone amplifier features "pop-free" power-on/off, a mute control, and it delivers 50mW of power into 16. The AK4368 is packaged in a 41-pin BGA package, deal for portable applications. FEATURE DAC Multi-bit Sampling Rate - 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz On chip perfect filtering 8 times FIR interpolator - Passband: 20kHz - Passband Ripple: 0.02dB - Stopband Attenuation: 54dB Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz PLL: - Input Frequency: 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz, 14.4MHz, 13MHz, 12MHz and 11.2896MHz - Input Level: AC Couple Input Available Audio I/F Format: MSB First, 2's Compliment - I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified - Master/Slave Mode Mixing: LR, LL, RR, (L+R)/2 Digital ALC Digital ATT Analog Mixing Circuit 3D Stereo Enhancement Stereo Lineout P Interface: 3-wire/I2C Bass Boost Function Headphone Amplifier - Output Power: 50mW x 2ch @16, 3.3V - S/N: 92dB@3.3V - Pop Noise Free at Power-ON/OFF and Mute Power Supply: 1.6V 3.6V Power Supply Current: 4.0mA @2.4V (HP-AMP no output) Ta: -30 85C Small Package: 41pin BGA (4mm x 4mm, 0.5mm pitch) MS0529-E-00 -1- 2006/07 ASAHI KASEI [AK4368EG] PVDD PVSS MCKO MCKI VCOC LIN MIN BICK LRCK SDATA DVDD DVSS AVDD Audio Interface PLL VCOM DAC (Lch) AVSS VCOM HDP Amp MUTE HPL ALC DEM ATT Bass Boost Digital Filter 3D Stereo Enhancement LOUT 3DCAP1 3DCAP2 3DCAP3 ROUT HDP Amp PDN I2C CAD0/CSN SCL/CCLK SDA/CDTI Serial I/F DAC (Rch) MUTE HPR HVDD HVSS MUTET RIN Figure 1. Block Diagram MS0529-E-00 -2- 2006/07 ASAHI KASEI [AK4368EG] Ordering Information AK4368EG AKD4368 -30 +85C 41pin BGA (0.5mm pitch) Evaluation board for AK4368 Pin Layout 7 6 5 AK4368EG 4 3 2 1 Top View A B C D E F G 7 6 5 4 3 2 1 NC HPL MIN RIN VCOC PVDD NC A HPR HVSS NC NC LIN PVSS MCKO B HVDD AVSS AVDD MUTET VCOM ROUT LOUT NC 3DCAP2 3DCAP3 NC 3DCAP1 NC CAD0/ CSN SCL/ CCLK NC G Top View NC DVSS DVDD C I2C MCKI D LRCK BICK E PDN NC SDATA SDA/ CDTI F MS0529-E-00 -3- 2006/07 ASAHI KASEI [AK4368EG] Comparison with AK4365 and AK4367 Parameter PLL Input Frequency AK4365 19.8/19.68/19.2/15.36/ 14.4/13/12/11.2896MHz AK4367 N/A N/A 24bit Right justified 16/20/24bit Left justified I 2S N/A N/A N/A Mono 3-wire/I2C +16dB (L+R)/2 50mW 2.2 3.6V 20QFN(4.2mm x 4.2mm) AK4368 27/26/19.8/19.68/19.2/ 15.36/14.4/13/12/11.2896 MHz 8/11.025/12/16/22.05/24/3 2/44.1/48kHz Sampling Frequency at PLL 8/11.025/16/22.05/24/32/ mode 44.1/48kHz 20bit Right justified Audio I/F Format 16/20bit Left justified I2S Master mode Available ALC N/A 3D Stereo Enhancement N/A Line Output Mono 3-wire P I/F Bass Boost +6dB Mixing (L+R)/2 HP-Amp Output Power 10mW Power Supply Voltage 2.7 3.3V Package 28QFN(5.2mm x 5.2mm) Available Available Available Stereo LL, RR, (L+R)/2 50mW 1.6 3.6V 41BGA(4mm x 4mm) MS0529-E-00 -4- 2006/07 ASAHI KASEI [AK4368EG] PIN/FUNCTION No. B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 G3 F4 G5 F6 G6 F7 E6 E7 D7 C6 D6 C7 B6 B7 A6 A5 A4 B3 A3 B2 A2 Pin Name MCKO DVSS DVDD I2C MCKI LRCK BICK SDATA SDA CDTI SCL CCLK CAD0 CSN PDN 3DCAP1 3DCAP2 3DCAP3 LOUT ROUT VCOM AVDD AVSS MUTET HVDD HVSS HPR HPL MIN RIN LIN VCOC PVSS PVDD I/O O I I I/O I/O I I/O I I I I I I O O O O O O O O O I I I O Function Master Clock Output Digital Ground Digital Power Supply Control Mode Select "H": I2C Bus, "L": 3-wire Serial Master Clock Input L/R Clock This clock determines which audio channel is currently being input on SDATA pin. Serial Bit Clock This clock is used to latch audio data. Audio Serial Data Input Control Data Input/Output (I2C pin = "H") Control Data Input (I2C pin = "L") Control Data Clock (I2C pin = "H") Control Data Clock (I2C pin = "L") Chip Address 0 Select (I2C pin = "H") Control Data Chip Select (I2C pin = "L") Power-down & Reset When "L", the AK4368 is in power-down mode and is held in reset. The AK4368 should always be reset upon power-up. Capacitor Connect Pin 1 for 3D Stereo Enhancement Connected to 3DCAP2 pin with 4.7nF capacitor in series. Capacitor Connect Pin 2 for 3D Stereo Enhancement Connected to 3DCAP1 pin with 4.7nF capacitor in series and connected to 3DCAP3 pin with 470nF capacitor in series. Capacitor Connect Pin 1 for 3D Stereo Enhancement Connected to 3DCAP2 pin with 470nF capacitor in series. Lch Analog Output Rch Analog Output Common Voltage Output Normally connected to AVSS pin with a 2.2F electrolytic capacitor. Analog Power Supply Analog Ground Mute Time Constant Control Connected to AVSS pin with a capacitor for mute time constant. Power Supply Pin for Headphone Amp Ground for Headphone Amp Rch Headphone Amp Output Lch Headphone Amp Output Mono Analog Input Rch Analog Input Lch Analog Input Output for Loop Filter of PLL Circuit This pin should be connected to AVSS with one resistor and one capacitor in series. Ground for PLL. Connected to AVSS. Power Supply for PLL. Normally connected to AVDD. MS0529-E-00 -5- 2006/07 ASAHI KASEI [AK4368EG] No. A1 A7 B4 B5 C3 F3 F5 G1 G4 G7 Pin Name NC I/O - Function No Connect Pin No internal bonding. These pins should be connected to ground or open. Note: All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not be left floating. Note: MCKI pin can be left floating only when PDN pin = "L". Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name LOUT, ROUT, MUTET, HPR, HPL, MIN, RIN, LIN CAD0 MCKO Setting These pins should be open. This pin should be connected to DVSS. This pin should be open. MS0529-E-00 -6- 2006/07 ASAHI KASEI [AK4368EG] ABSOLUATE MAXIMUM RATING (AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol Min max Power Supplies Analog AVDD 4.6 -0.3 Digital DVDD 4.6 -0.3 PLL PVDD 4.6 -0.3 HP-Amp HVDD 4.6 -0.3 |AVSS - DVSS| (Note 2) 0.3 GND1 |AVSS - HVSS| (Note 2) 0.3 GND2 |AVSS - PVSS| (Note 2) 0.3 GND3 Input Current (any pins except for supplies) IIN 10 Analog Input Voltage (Note 3) VINA AVDD+0.3 or 4.6 -0.3 Digital Input Voltage (Note 4) VIND DVDD+0.3 or 4.6 -0.3 Ambient Temperature Ta 85 -30 Storage Temperature Tstg 150 -65 Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS, HVSS and PVSS must be connected to the same analog ground plane. Note 3. MIN, LIN and RIN pins. Note 4. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN and I2C pins. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Units V V V V V V V mA V V C C RECOMMEND OPERATING CONDITIONS (AVSS, DVSS, HVSS, PVSS=0V; Note 1) Parameter Symbol min typ Power Supplies Analog AVDD 1.6 2.4 Digital DVDD 1.6 2.4 PLL PVDD 1.6 2.4 HP-Amp HVDD 1.6 2.4 Difference1 0 AVDD-PVDD -0.3 Difference2 0 AVDD-HVDD -0.3 Note 1. All voltages with respect to ground. * AKM assumes no responsibility for usage beyond the conditions in this datasheet. Max 3.6 AVDD 3.6 3.6 +0.3 +0.3 Units V V V V V V MS0529-E-00 -7- 2006/07 ASAHI KASEI [AK4368EG] ANALOG CHARACTERISTICS (Ta=25C; AVDD=PVDD=DVDD=HVDD=2.4V, AVSS=PVSS=DVSS=HVSS=0V; fs=44.1kHz; EXT mode; BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz 20kHz; Headphone-Amp: Load impedance is a serial connection with RL =16 and CL=220F. (Refer to Figure 48); unless otherwise specified) Parameter min typ Max Units 24 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 5) Analog Output Characteristics THD+N dB -3dBFS Output, 2.4V, Po=10mW@16 -50 -40 -4.8dBFS Output, 3.3V, dB -20 Po=50mW@16 HPG bit="1" 82 90 dB D-Range -60dBFS Output, A-weighted 92 dB -60dBFS Output, A-weighted, 3.3V S/N A-weighted, 2.4V 82 90 dB A-weighted, 3.3V 92 dB Interchannel Isolation 60 80 dB DC Accuracy Interchannel Gain Mismatch 0.3 0.5 dB Gain Drift 200 ppm/C Load Resistance (Note 6) 16 Load Capacitance 300 pF Output Voltage -3dBFS Output (Note 7) 1.01 1.13 1.25 Vpp -4.8dBFS Output, 3.3V, 0.89 Vrms Po=50mW@16 HPG bit="1" Stereo Line Output: (LOUT/ROUT pins, RL=10k) (Note 8) Analog Output Characteristics: THD+N 0dBFS Output dB -60 -50 S/N A-weighted 80 87 dB DC Accuracy Gain Drift 200 ppm/C Load Resistance (Note 6) 10 k Load Capacitance 25 pF Output Voltage 0dBFS Output (Note 9) 1.32 1.47 1.61 Vpp Output Volume: (LOUT/ROUT pins) Step Size 1 2 3 dB Gain Control Range 0 dB -30 Note 5. DACHL=DACHR bits = "1", MINHL=MINHR=LINHL=RINHR bits = "0". Note 6. AC load. Note 7. Output voltage is proportional to AVDD voltage. Vout = 0.47 x AVDD(typ)@-3dBFS. Note 8. DACL=DACR bits = "1", MINL=MINR=LINL=RINR bits = "0". Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.61 x AVDD(typ)@0dBFS. MS0529-E-00 -8- 2006/07 ASAHI KASEI [AK4368EG] Parameter LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance (See Figure 23, Figure 24.) LIN pin LINHL bit = "1", LINL bit = "1" LINHL bit = "1", LINL bit = "0" LINHL bit = "0", LINL bit = "1" RIN pin RINHR bit = "1", RINR bit = "1" RINHR bit = "1", RINR bit = "0" RINHR bit = "0", RINR bit = "1" MIN pin MINHL=MINHR=MINL=MINR bits = "1" MINHL bit = "1", MINHR=MINL=MINR bits = "0" MINHR bit = "1", MINHL=MINL=MINR bits = "0" MINL bit = "1", MINHL=MINHR=MINR bits = "0" MINR bit = "1", MINHL=MINHR=MINL bits = "0" Gain LIN/MINLOUT, RIN/MIN ROUT LIN/MINHPL, RIN/MIN HPR Power Supplies Power Supply Current Normal Operation (PDN pin = "H") (Note 10) AVDD+PVDD+DVDD HVDD Power-Down Mode (PDN pin = "L") (Note 11) min typ max Units 35 35 17 -1 -0.24 50 100 100 50 100 100 25 100 100 100 100 0 +0.76 +1 +1.76 k k k k k k k k k k k dB dB - 3.8 1.2 1 5.5 2.5 100 mA mA A Note 10. PMDAC=PMHPL=PMHPR=PMLO bits = "1", MUTEN bit = "1", MCKO bit = "0" and HP-Amp output is off. When PMDAC=PMHPL=PMHPR bits = "1" and PMLO bit= "0", total power supply current (AVDD+PVDD+DVDD+HVDD) is 4.0mA. Note 11. All digital input pins including clock pins (MCKI, BICK and LRCK) are held at DVSS. MS0529-E-00 -9- 2006/07 ASAHI KASEI [AK4368EG] FILTER CHARACTERISTICS (Ta=25C; AVDD, DVDD, PVDD, HVDD=1.6 3.6V; fs=44.1kHz; De-emphasis = "OFF") Parameter Symbol min typ max Units DAC Digital Filter: (Note 12) Passband (Note 13) PB 0 20.0 kHz -0.05dB 22.05 kHz -6.0dB Stopband (Note 13) SB 24.1 kHz Passband Ripple PR dB 0.02 Stopband Attenuation SA 54 dB Group Delay (Note 14) GD 22 1/fs Group Delay Distortion 0 GD s DAC Digital Filter + Analog Filter: (Note 12) (Note 15) Frequency Response FR dB 0 20.0kHz 0.5 Analog Filter: (Note 16) Frequency Response FR dB 0 20.0kHz 1.0 BOOST Filter: (Note 15) (Note 17) Frequency Response 20Hz FR dB 5.76 MIN 100Hz dB 2.92 1kHz dB 0.02 20Hz FR dB 10.80 MID 100Hz dB 6.84 1kHz dB 0.13 20Hz FR dB 16.06 MAX 100Hz dB 10.54 1kHz dB 0.37 Note 12. BOOST OFF (BST1-0 bit = "00") Note 13. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@0.05dB), SB=0.546*fs(@-54dB). Note 14. This is the calculated delay time caused by digital filtering. This time is measured from the setting of the 24bit data of both channels to the input registers to the output of the analog signal. Note 15. DAC HPL, HPR, LOUT, ROUT Note 16. MIN HPL/HPR/LOUT/ROUT, LIN HPL/LOUT, RIN HPR/ROUT Note 17. These frequency responses scale with fs. If high-level signal is input, the output clips at low frequency. Boost Filter (fs=44.1kHz) 20 MAX 15 MID Gain [dB] 10 MIN 5 0 -5 10 100 Frequency [Hz] 1000 10000 Figure 2. Boost Frequency (fs=44.1kHz) MS0529-E-00 - 10 - 2006/07 ASAHI KASEI [AK4368EG] DC CHARACTERISTICS (Ta=25C; AVDD, DVDD, PVDD, HVDD=1.6 3.6V) Parameter Symbol Min High-Level Input Voltage 2.2VDVDD3.6V VIH 70%DVDD 1.6VDVDD<2.2V VIH 80%DVDD Low-Level Input Voltage 2.2VDVDD3.6V VIL 1.6VDVDD<2.2V VIL Input Voltage at AC Coupling (Note 18) VAC 0.4 High-Level Output Voltage VOH (Iout=-200A) DVDD-0.2 Low-Level Output Voltage VOL (Except SDA pin: Iout=200A) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin Note 18. Only MCKI pin. (Figure 48) typ - max 30%DVDD 20%DVDD 0.2 0.4 10 Units V V V V Vpp V V V A MS0529-E-00 - 11 - 2006/07 ASAHI KASEI [AK4368EG] SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD, PVDD, HVDD=1.6 3.6V; CL = 20pF; unless otherwise specified) Parameter Symbol min typ Master Clock Input Timing Frequency (PLL mode) fCLK 11.2896 (EXT mode) fCLK 2.048 Pulse Width Low (Note 19) tCLKL 0.4/fCLK Pulse Width High (Note 19) tCLKH 0.4/fCLK AC Pulse Width (Note 20) tACW 18.5 LRCK Timing Frequency fs 8 44.1 Duty Cycle: Slave Mode Duty 45 Master Mode Duty 50 MCKO Output Timing (PLL mode) Frequency fCLKO 0.256 Duty Cycle (Except fs=32kHz, PS1-0= "00") dMCK 40 (fs=32kHz, PS1-0= "00") dMCK 33 Serial Interface Timing (Note 21) Slave Mode (M/S bit = "0"): BICK Period tBCK 312.5 BICK Pulse Width Low tBCKL 100 Pulse Width High tBCKH 100 tLRB 50 LRCK Edge to BICK "" (Note 22) tBLR 50 BICK "" to LRCK Edge (Note 22) SDATA Hold Time tSDH 50 SDATA Setup Time tSDS 50 Master Mode (M/S bit = "1"): BICK Frequency (BF bit = "1") fBCK 64fs (BF bit = "0") fBCK 32fs BICK Duty dBCK 50 tMBLR BICK "" to LRCK -50 SDATA Hold Time tSDH 50 SDATA Setup Time tSDS 50 Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN "H" Time tCSW 150 tCSS 50 CSN "" to CCLK "" tCSH 50 CCLK "" to CSN "" max 27 12.288 48 55 12.288 60 - Units MHz MHz ns ns ns kHz % % MHz % % 50 - ns ns ns ns ns ns ns Hz Hz % ns ns ns ns ns ns ns ns ns ns ns Note 19. Except AC coupling. Note 20. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 3.) Note 21. Refer to "Serial Data Interface". Note 22. BICK rising edge must not occur at the same time as LRCK edge. MS0529-E-00 - 12 - 2006/07 ASAHI KASEI [AK4368EG] Parameter Control Interface Timing (I2C Bus mode): (Note 23) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 24) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Capacitive Load on Bus Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 25) Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb tSP tPD min 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 150 typ - max 400 0.3 0.3 400 50 - Units kHz s s s s s s s s s s pF ns ns Note 23. I2C is a registered trademark of Philips Semiconductors. Note 24. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 25. The AK4368 can be reset by bringing PDN pin = "L" to "H" only upon power up. MS0529-E-00 - 13 - 2006/07 ASAHI KASEI [AK4368EG] Timing Diagram 1/fCLK 1000pF MCKI Input 100k DVSS Measurement Point tACW tACW VAC DVSS Figure 3. MCKI AC Coupling Timing 1/fCLK VIH VIL tCLKH tCLKL MCKI 1/fs VIH VIL LRCK tBCK VIH VIL tBCKH tBCKL BICK MCKO tH tL dMCK=tH/(tH+tL) or tL/(tH+tL) 50% DVDD Figure 4. Clock Timing MS0529-E-00 - 14 - 2006/07 ASAHI KASEI [AK4368EG] LRCK tBLR tLRB VIH VIL BICK tSDS tSDH VIH VIL SDATA VIH VIL Figure 5. Serial Interface Timing (Slave Mode) LRCK 50%DVDD tMBLR BICK tSDH 50%DVDD tSDS SDATA VIH VIL Figure 6. Serial Interface Timing (Master mode) MS0529-E-00 - 15 - 2006/07 ASAHI KASEI [AK4368EG] VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL CCLK CDTI C1 C0 R/W A4 Figure 7. WRITE Command Input Timing tCSW VIH CSN VIL tCSH CCLK VIH VIL CDTI D3 D2 D1 D0 VIH VIL Figure 8. WRITE Data Input Timing VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop Figure 9. I2C Bus Mode Timing tPD PDN VIL Figure 10. Power-down & Reset Timing MS0529-E-00 - 16 - 2006/07 ASAHI KASEI [AK4368EG] OPERATION OVERVIEW System Clock 1) PLL mode (PMPLL bit = "1") A fully integrated analog phase locked loop (PLL) generates a clock that is selected by PLL3-0 and FS3-0 bits (refer to Table 1 and Table 2). MCKO output frequency can be controlled by PS1-0 bits (Table 3). MCKO output can be enabled by controlling the MCKO bit. The PLL lock time is referred to Table 1. When changing the sampling frequency during normal operation (PMDAC bit = "1"), the change should occur after the input is muted by SMUTE bit = "1", or the input is set to "0" data. The M/S bit selects either master or slave mode. When the M/S bit = "1" master mode is selected and "0" selects slave mode. When the AK4368 is in power-down mode (PDN pin = "L") and then exits the reset state, the AK4368 is in slave mode. After exiting the reset state, the AK4368 goes to master mode by changing the M/S bit to "1". In master mode, when an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz, 19.8MHz, 26MHz, 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit (Figure 11). 27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz AK4368 MCKI MCKO BICK LRCK SDATA DSP or P 256fs/128fs/64fs/32fs 32fs, 64fs 1fs MCLK BCLK LRCK SDTO Figure 11. PLL Master Mode When the AK4368 is used in the master mode, LRCK and BICK pins are in a floating state until the M/S bit becomes "1". LRCK and BICK pins of the AK4368 should be pulled-down or pulled-up by a resistor (about 100k) externally to avoid the floating state. In master mode (M/S bits = "1"), LRCK and BICK pins output "L" before the PLL is locked by setting PMPLL = PMDAC bits = "0" "1". At that time, MCKO pin outputs an abnormal frequency clock at MCKO bit = "1". When MCKO bit = "0", MCKO pin outputs "L". After the PLL is locked, LRCK and BICK start to output the clocks (Table 4). MS0529-E-00 - 17 - 2006/07 ASAHI KASEI [AK4368EG] In slave mode, a reference clock of PLL is selected among the input clocks to BICK or LRCK pin. The required clock to the AK4368 is generated by an internal PLL circuit. BICK and LRCK inputs should be synchronized with MCKO output (Figure 12). AK4368 MCKI MCKO BICK LRCK SDATA 27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz DSP or P 256fs/128fs/64fs/32fs 32fs ~ 64fs 1fs MCLK BCLK LRCK SDTO Figure 12. PLL Slave Mode In slave mode (M/S bit = "0"), the MCKO pin outputs an abnormal frequency clock when the MCKO bit = "1" before the PLL is locked by setting PMPLL = PMDAC bits = "0" "1". After the PLL is locked, the MCKO pin outputs the clock selected by Table 3. LRCK input should be synchronized with MCKI or MCKO in slave mode. LRCK and BICK should always be present whenever the AK4368 is in normal operation mode (PMDAC bit = "1"). If these clocks are not provided, the AK4368 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK4368 should be placed in power-down mode (PMDAC bit = "0"). Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15 PLL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 PLL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 Others PLL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 PLL0 0 1 0 1 0 1 0 1 0 1 MCKI 11.2896MHz 14.4MHz 12MHz 19.2MHz 15.36MHz 13MHz 19.68MHz 19.8MHz 26MHz 27MHz fs (Note 26) 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.1, 48 44.0995 10k 0 13MHz 48.0007 44.0995 10k 1 26MHz 48.0007 44.0995 0 19.8MHz 10k 47.9992 44.0995 10k 1 27MHz 47.9997 N/A N/A N/A Note 26. Type 1-4 frequency is indicated in Table 2. Table 1. MCKI Input Frequency (PLL mode) R and C of VCOC pin C[F] R[] 10k 22n 10k 22n 10k 47n 10k 22n 10k 22n 15k 330n 10k 47n 10k 47n 15k 330n 10k 47n 22n 22n 22n 22n N/A PLL Lock Time (typ) 20ms 20ms 20ms 20ms 20ms 100ms 20ms 20ms 100ms 20ms 20ms 20ms 20ms 20ms Default MS0529-E-00 - 18 - 2006/07 ASAHI KASEI [AK4368EG] Mode 0 1 2 4 5 6 8 9 10 3, 7, 11-15 FS3 0 0 0 0 0 0 1 1 1 FS2 0 0 0 1 1 1 0 0 0 FS1 0 0 1 0 0 1 0 0 1 FS0 0 1 0 0 1 0 0 1 0 fs Type 1 48kHz 24kHz 12kHz 32kHz 16kHz 8kHz 44.1kHz 22.05kHz 11.025kHz N/A Type 2 48.0007kHz 24.0004kHz 12.0002kHz 32.0005kHz 16.0002kHz 8.0001kHz 44.0995kHz 22.0498kHz 11.0249kHz N/A Type 3 47.9992kHz 23.9996kHz 11.9998kHz 31.9994kHz 15.9997kHz 7.9999kHz 44.0995kHz 22.0498kHz 11.0249kHz N/A Type 4 47.9997kHz 23.9999kHz 11.9999kHz 31.9998kHz 15.9999kHz 7.9999kHz 44.0995kHz 22.0498kHz 11.0249kHz N/A Default Others Table 2. Sampling Frequency (PLL mode) PS1 PS0 MCKO 0 0 256fs Default 0 1 128fs 1 0 64fs 1 1 32fs Table 3. MCKO frequency (PLL mode, MCKO bit = "1") Master Mode (M/S bit = "1") Power Up Power Down PLL Unlock (PMDAC bit= PMPLL bit= "1") (PMDAC bit= PMPLL bit= "0") Refer to Note 26. Type 1-4 MCKI pin Refer to Note 26. Type 1-4 Input or frequency is indicated in frequency is indicated in Table fixed to "L" or "H" Table 2. 2. Table 1. Table 1. MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "0": "L" MCKO bit = "1": Output MCKO bit = "1": Unsettling BICK pin BF bit = "1": 64fs output "L" "L" BF bit = "0": 32fs output LRCK pin Output "L" "L" Table 4. Clock Operation in Master mode (PLL mode) Power Up (PMDAC bit= PMPLL bit= "1") MCKI pin Refer to Note 26. Type 1-4 frequency is indicated in Table 2. Table 1. MCKO pin MCKO bit = "0": "L" MCKO bit = "1": Output BICK pin Input LRCK pin Input Slave Mode (M/S bit = "0") Power Down PLL Unlock (PMDAC bit= PMPLL bit= "0") Input or Refer to Note 26. Type 1-4 fixed to "L" or "H" frequency is indicated in Table 2. Table 1. "L" MCKO bit = "0": "L" MCKO bit = "1": Unsettling Fixed to "L" or "H" externally Input or Fixed to "L" or "H" externally Fixed to "L" or "H" externally Input or Fixed to "L" or "H" externally Table 5. Clock Operation in Slave mode (PLL mode) MS0529-E-00 - 19 - 2006/07 ASAHI KASEI [AK4368EG] 2) EXT mode (PMPLL bit = "0": Default) The AK4368 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to "0". In EXT mode, the master clock can directly input to the DAC via the MCKI pin without going through the PLL. In this case, the sampling frequency and MCKI frequency can be selected by FS3-0 bits (refer to Table 6). In EXT mode, PLL3-0 bits are ignored. MCKO output is enabled by controlling the MCKO bit. MCKO output frequency can be controlled by PS1-0 bits. If the sampling frequency is changed during normal operation of the DAC (PMDAC bit = "1"), the change should occur after the input is muted by SMUTE bit = "1", or the input is set to "0" data. LRCK and BICK are output from the AK4368 in master mode(Figure 13). The clock input to the MCKI pin should always be present whenever the DAC is in normal operation (PMDAC bit = "1"). If these clocks are not provided, the AK4368 may draw excessive current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = "0"). AK4368 MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDATA 32fs, 64fs 1fs MCLK BCLK LRCK SDTO DSP or P Figure 13. EXT Master Mode The external clocks required to operate the AK4368 in slave mode are MCKI, LRCK and BICK(Figure 14). The master clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter. All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode (PMDAC bit = "1"). If these clocks are not provided, the AK4368 may draw excessive current and will not operate properly, because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = "0"). AK4368 MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK SDATA 32fs ~ 64fs 1fs MCLK BCLK LRCK SDTO DSP or P Figure 14. EXT Slave Mode MS0529-E-00 - 20 - 2006/07 ASAHI KASEI [AK4368EG] Mode FS3 FS2 FS1 FS0 fs MCKI 0 0 0 0 0 256fs 8kHz 48kHz 1 0 0 0 1 512fs 8kHz 24kHz 2 0 0 1 0 1024fs 8kHz 12kHz 4 0 1 0 0 256fs 8kHz 48kHz 5 0 1 0 1 512fs 8kHz 24kHz 6 0 1 1 0 1024fs 8kHz 12kHz 8 1 0 0 0 256fs Default 8kHz 48kHz 9 1 0 0 1 512fs 8kHz 24kHz 10 1 0 1 0 1024fs 8kHz 12kHz 3, 7, Others N/A N/A 11-15 Table 6. Relationship between Sampling Frequency and MCKI Frequency (EXT mode) PS1 PS0 MCKO 0 0 256fs Default 0 1 128fs 1 0 64fs 1 1 32fs Table 7. MCKO frequency (EXT mode, MCKO bit = "1") Master Mode (M/S bit = "1") Power Up (PMDAC bit = "1") Power Down (PMDAC bit = "0") MCKI pin Refer to Table 6. Input or fixed to "L" or "H" MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "1": Output BICK pin BF bit = "1": 64fs output "L" BF bit = "0": 32fs output LRCK pin Output "L" Table 8. Clock Operation in Master mode (EXT mode) Slave Mode (M/S bit = "0") Power Up (PMDAC bit = "1") Power Down (PMDAC bit = "0") MCKI pin Refer to Table 6. Input or fixed to "L" or "H" MCKO pin MCKO bit = "0": "L" "L" MCKO bit = "1": Output BICK pin Input Fixed to "L" or "H" externally LRCK pin Input Fixed to "L" or "H" externally Table 9. Clock Operation in Slave mode (EXT mode) For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by using higher frequency for MCKI. Table 10 shows DR and S/N when the DAC output is to the HP-amp. DR, S/N (BW=20kHz, A-weight) fs=8kHz fs=16kHz 256fs 56dB 75dB 512fs 75dB 90dB 1024fs 90dB N/A Table 10. Relationship between MCKI frequency and DR (and S/N) of HP-amp (2.4V) MCKI MS0529-E-00 - 21 - 2006/07 ASAHI KASEI [AK4368EG] Serial Data Interface The AK4368 interfaces with external systems via the SDATA, BICK and LRCK pins. Five data formats are available, selected by setting the DIF2, DIF1 and DIF0 bits (Table 11). Mode 0 is compatible with existing 16-bit DACs and digital filters. Mode 1 is a 20-bit version of Mode 0. Mode 4 is a 24-bit version of Mode 0. Mode 2 is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In Modes 2 and 3 with BICK48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2's complement format. When master mode and BICK=32fs(BF bit = "0"), the AK4368 cannot be set to Mode 1 or Mode 2. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 Format BICK 0: 16bit, LSB justified 32fs BICK 64fs 1: 20bit, LSB justified 40fs BICK 64fs 2: 24bit, MSB justified 48fs BICK 64fs 3: I2S Compatible BICK=32fs or 48fs BICK 64fs 4: 24bit, LSB justified 48fs BICK 64fs Table 11. Audio Data Format Figure Figure 15 Figure 16 Figure 17 Figure 18 Figure 16 Default LRCK BICK (32fs) SDATA Mode 0 BICK SDATA Mode 0 15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15 14 Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0 Lch Data Rch Data Figure 15. Mode 0 Timing (LRP = BCKP bits = "0") LRCK BICK SDATA Mode 1 SDATA Mode 4 Don't care 19:MSB, 0:LSB Don't care 23:MSB, 0:LSB 23 22 21 20 19 0 Don't care 19 0 19 0 Don't care 23 22 21 20 19 0 Lch Data Rch Data Figure 16. Mode 1, 4 Timing (LRP = BCKP bits = "0") MS0529-E-00 - 22 - 2006/07 ASAHI KASEI [AK4368EG] LRCK Lch Rch BICK SDATA 16bit SDATA 20bit SDATA 24bit Figure 17. Mode 2 Timing (LRP = BCKP bits = "0") 23 22 8 3 4 1 0 Don't care 23 22 8 3 4 1 0 Don't care 23 22 19 18 4 1 0 Don't care 19 18 4 1 0 Don't care 19 18 15 14 0 Don't care Don't care 15 14 0 15 14 LRCK BICK SDATA 16bit SDATA 20bit SDATA 24bit 15 14 Lch Rch 0 Don't care 15 14 0 Don't care 15 19 18 4 1 0 Don't care 19 18 4 1 0 Don't care 19 23 22 8 3 4 1 0 Don't care 23 22 8 3 4 1 0 Don't care 23 BICK (32fs) SDATA 16bit 0 15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15 Figure 18. Mode 3 Timing (LRP = BCKP bits = "0") MS0529-E-00 - 23 - 2006/07 ASAHI KASEI [AK4368EG] ALC Operation The ALC (Automatic Level Control) is controlled by the ALC block when ALC bit is "1". When ALC bit = "0", the gain of ALC block is fixed to 0dB. [1] ALC Limiter Operation During ALC limiter operation, when either the left or right channel exceeds the ALC limiter detection level (-6.0dBFS), the volume of both channel (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (LMAT1-0 bits, Table 13). The volume is changed by the ALC limiter operation at the individual zero crossing points of the left and right channels, or at the zero crossing timeout. ROTM1-0 bits set the zero crossing timeout period of both the ALC limiter and recovery operation (Table 12). Then the volume is set to the same value for both channels. ROTM1 0 0 1 1 ROTM0 0 1 0 1 ALC Recovery Operation Waiting Period, Zero Crossing Timeout Period fs=16kHz fs=22.05kHz fs=24kHz fs=32kHz fs=44.1kHz fs=48kHz 1024/fs 64ms 46ms 43ms 32ms 23ms 21ms 2048/fs 128ms 93ms 85ms 64ms 46ms 43ms 4096/fs 256ms 186ms 171ms 128ms 93ms 85ms Reserved Table 12. ALC Recovery Operation Waiting Period, Zero Crossing Timeout Period ALC Limiter ATT Step ALC Output ALC Output ALC Output ALC Output 0dBFS +6dBFS +12dBFS -6.0dBFS 1 1 1 1 Default 2 2 2 2 2 2 4 4 2 4 4 8 Table 13. ALC Limiter ATT Step Default LMAT1 0 0 1 1 LMAT0 0 1 0 1 MS0529-E-00 - 24 - 2006/07 ASAHI KASEI [AK4368EG] [2] ALC Recovery Operation The ALC recovery operation waits for the ROTM1-0 bits (Table 12) to be set after completing the ALC limiter operation. If the input signal does not exceed "ALC recovery waiting counter reset level" (-8.5dBFS) during the wait time, the ALC recovery operation is executed. The volume is automatically incremented by the RATT bit (Table 14) up to the set reference level (REF7-0 bits, Table 15), with zero crossing detection with a timeout period set by the ROTM1-0 bits (Table 12). Then the volume is set to the same level for both channels. The ALC recovery operation is executed at a period set by the ROTM1-0 bits. When a zero cross is detected for both channels during the wait period set by the ROTM1-0 bits, the ALC recovery operation waits until ROTM1-0 period and the next recovery operation is executed. During ALC recovery operation or recovery waiting, the ALC limiter operation immediately starts if either channel exceeds the ALC limiter detection level (-6.0dBFS). When "ALC recovery waiting counter reset level (-8.5dBFS) Output Signal < ALC limiter detection level (-6.0dBFS)" during the ALC recovery operation, the wait timer of the ALC recovery operation is reset. When the "ALC recovery waiting counter reset level (-8.5dBFS) > Output Signal", the wait timer of the ALC recovery operation starts. The ALC operation corresponds to impulse noise. When impulse noise is input, the ALC recovery operation executes faster than a normal recovery operation. RATT GAIN STEP 0 1 Default 1 2 Table 14. ALC Recovery GAIN Step REF7-0 GAIN(dB) FFH : Reserved C2H C1H +18.0 C0H +17.625 BFH +17.25 : : 92H +0.375 91H 0 Default 90H -0.375 : : 73H -11.25 72H -11.625 71H -12.0 70H : Reserved 00H Table 15. Reference Level for ALC Recovery operation MS0529-E-00 - 25 - 2006/07 ASAHI KASEI [AK4368EG] [3] Example of ALC Operation Register Name ROTM1-0 REF7-0 LMAT1-0 RATT ALC fs=16kHz Data Operation Zero crossing timeout period 00 64ms Maximum gain at recovery operation C1H +18dB Limiter ATT step 00 1 step Recovery GAIN step 0 1 step ALC enable 1 Enable Table 16. Example of the ALC setting Comment fs=44.1kHz Operation 46ms +18dB 1 step 1 step Enable Data 01 C1H 00 0 1 The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = "0" or PMDAC bits = "0". * LMAT1-0, ROTM1-0, RATT, REF7-0 ALC = OFF Example: Recovery Cycle = 46ms@44.1kHz Limiter and Recovery Step = 1 WR (REF7-0) Maximum Gain = +18dB ALC bit = "1" WR (LMAT1-0, RATT, ROTM1-0; ALC= "1") ALC Operation Note: WR: Write (1) Addr=0AH, Data=C1H (2) Addr=0BH, Data=30H Figure 19. Registers set-up sequence at ALC operation MS0529-E-00 - 26 - 2006/07 ASAHI KASEI [AK4368EG] Digital Attenuator The AK4368 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to -127dB or MUTE) for each channel (Table 17). At DATTC bit = "1", ATTL7-0 bits control both channel's attenuation levels. At DATTC bit = "0", ATTL7-0 bits control the left channel level and ATTR7-0 bits control the right channel level. ATTL7-0 Attenuation ATTR7-0 FFH 0dB FEH -0.5dB FDH -1.0dB FCH -1.5dB : : : : 02H -126.5dB 01H -127.0dB 00H Default MUTE (-) Table 17. Digital Volume ATT values The ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 18). When the ATS bit = "0", a soft transition between the set values occurs(1062 levels). It takes 1061/fs (24ms@fs=44.1kHz) from FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is "0". When the PMDAC returns to "1", the ATTs fade to their current value. The digital attenuator is independent of the soft mute function. ATT speed 0dB to MUTE 1 step 0 1061/fs 4/fs Default 1 7424/fs 29/fs Table 18. Transition time between set values of ATT7-0 bits ATS MS0529-E-00 - 27 - 2006/07 ASAHI KASEI [AK4368EG] Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to "1", the output signal is attenuated by - during the ATT_DATAxATT transition time (Table 18) from the current ATT level. When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATAxATT transition time. If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and is returned to the ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATS bit ATT Level Attenuation (1) ATS bit (1) (3) - GD (2) Analog Output GD Figure 20. Soft Mute Function Notes: (1) ATT_DATAxATT transition time (Table 18). For example, this time is 3712LRCK cycles (3712/fs) at ATS bit = "1" and ATT_DATA = "128". (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and it is returned to the ATT level by the same cycle. MS0529-E-00 - 28 - 2006/07 ASAHI KASEI [AK4368EG] De-emphasis Filter The AK4368 includes a digital de-emphasis filter (tc = 50/15s), using an IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 19). DEM1 bit DEM0 bit De-emphasis 0 0 44.1kHz 0 1 OFF Default 1 0 48kHz 1 1 32kHz Table 19. De-emphasis Filter Frequency Select Bass Boost Function By controlling the BST1-0 bits, a low frequency boost signal can be output from DAC. The setting value is common for both channels (Table 20). BST1 bit BST0 bit BOOST 0 0 OFF 0 1 MIN 1 0 MID 1 1 MAX Table 20. Low Frequency Boost Select Default Mixing Function MONO1-0 bits select the digital data mixing for the DAC (Table 21). MONO1 bit 0 0 1 1 MONO0 bit Lch 0 L 1 L 0 R 1 (L+R)/2 Table 21. Mixer Setting Rch R L R (L+R)/2 Default System Reset The AK4368 should be reset once by bringing PDN pin "L" upon power-up. After exiting reset, VCOM, DAC, HPL, HPR, LOUT and ROUT switch to the power-down state. The contents of the control register are maintained until the reset is completed. The DAC exits reset and power down states by MCKI after the PMDAC bit is changed to "1". The DAC is in power-down mode until MCKI is input. MS0529-E-00 - 29 - 2006/07 ASAHI KASEI [AK4368EG] Headphone Output (HPL, HPR pins) The power supply voltage for the headphone-amp is supplied from the HVDD pin and is centered on the MUTET voltage. The headphone-amp output load resistance is 16 (min). When the MUTEN bit is "1" at PMHPL=PMHPR= "1", the common voltage rises to 0.475 x HVDD. When the MUTEN bit is "0", the common voltage of the headphone-amp falls and the outputs (HPL and HPR pins) go to HVSS. tr: Rise Time up to VCOM/2 70k x C (typ) tf: Fall Time down to VCOM/2 60k x C (typ) Table 22. Headphone-Amp Rise/Fall Time [Example] : Capacitor between the MUTET pin and ground = 1F: Rise time up to VCOM/2: tr = 70k x 1 = 70ms(typ). Fall time down to VCOM/2: tf = 60k x 1 = 60ms(typ). When the PMHPL and PMHPR bits are "0", the headphone-amp is powered-down, and the outputs (HPL and HPR pins) go to HVSS. PMHPL/R bit MUTEN bit VCOM VCOM/2 tf (3) (4) HPL/R pin tr (1) (2) Figure 21. Power-up/Power-down Timing for the Headphone-Amp (1) Headphone-amp power-up (PMHPL and PMHPR bits = "1"). The outputs are still at HVSS. (2) Headphone-amp common voltage rises up (MUTEN bit = "1"). Common voltage of the headphone-amp is rising. This rise time depends on the capacitor value connected with the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ) when the capacitor value on MUTET pin is "C". (3) Headphone-amp common voltage falls down (MUTEN bit = "0"). Common voltage of the headphone-amp is falling to HVSS. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ) when the capacitor value on MUTET pin is "C". (4) Headphone-amp power-down (PMHPL, PMHPR bits = "0"). The outputs are at HVSS. If the power supply is switched off or the headphone-amp is powered-down before the common voltage goes to HVSS, some pop noise may occur. MS0529-E-00 - 30 - 2006/07 ASAHI KASEI [AK4368EG] The cut-off frequency of the headphone-amp output depends on the external resistor and capacitor used. Table 23 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16. Output powers are shown at AVDD = 2.4, 3.0 and 3.3V. The output voltage of the headphone is 0.47 x AVDD (Vpp) @-3dBFS. HP-AMP R C Headphone 16 AK4368 Figure 22. External Circuit Example of Headphone Output Power [mW] R [] C [F] 220 100 100 47 100 47 fc [Hz] BOOST=OFF fc [Hz] BOOST=MIN HPG=0, 0dB HPG=1, -4.8dB 3.3V 50 25 13 0 6.8 16 2.4V 3.0V 3.3V 45 17 20 31 38 100 43 70 28 10 15 18 149 78 50 19 5 8 9 106 47 Table 23. Relationship of external circuit, output power and frequency response DACHL, LINHL, MINHL, DACHR, RINHR and MINHR bits set the path, respectively. When the HPG bit is "0"(R1= 100k), the gain is +0.76dB(typ) for all paths. When HPG bit is "1"(R1= 50k), the DAC path gain is +6.76dB(typ). 100k(typ) 100k(typ) 1.09R2 LIN/RIN pin LINHL/RINHR bit 100k(typ) MIN pin MINHL/MINHR bit R1 - + R2 - + HP-Amp HPL/HPR pin DACL/DACR DACHL/DACHR bit Figure 23. Summation circuit for headphone amp output (HPG bit = "0") MS0529-E-00 - 31 - 2006/07 ASAHI KASEI [AK4368EG] Stereo Line Output (LOUT, ROUT pins) The common voltage is 0.475 x AVDD. The load resistance is 10k(min). When the PMLO bit is "1", the stereo line output is powered-up. DACL, LINL, MINL, DACR, RINR and MINR bits set the path, respectively. When LOG bit is "0"(R1= 100k) and ATTS3-0 bits is "0FH"(0dB), the gain is 0dB(typ) for all paths. When the LOG bit is "1"(R1= 50k), the DAC path gain is +6dB. 100k(typ) 100k(typ) R2 LIN/RIN pin LINL/RINR bit 100k(typ) MIN pin MINL/MINR bit R1 - + R2 - + LOUT/ROUT pin DACL/DACR DACL/DACR bit Figure 24. Summation circuit for stereo line output (LOG bit = "0") Analog Output Volume LOUT/ROUT volume is controlled by ATTS3-0 bits when LMUTE bit = "0" (0dB -30dB, 2dB step, Table 24). Pop noise occurs when ATTS3-0 bits are changed. ATTS3-0 Attenuation 0FH 0dB 0EH -2dB 0DH -4dB 0CH -6dB 0 : : : : 01H -28dB 00H -30dB 1 X MUTE Default Table 24. LOUT/ROUT Volume ATT values (x: Don't care) LMUTE MS0529-E-00 - 32 - 2006/07 ASAHI KASEI [AK4368EG] 3D Stereo Enhancement AK4368 features a 3D stereo enhancement function. 3D1-0 bits control the power management of the 3D function block (Table 25), and DP1-0 bits set the 3D depth (Table 26). 3D1-0 and MUTEN bits should not be changed to avoid pop noise for 50ms after 3D1-0 bits are changed. 4.7nF20% and 470nF20% capacitors should be connected at 3DCAP1, 3DCAP2 and 3DCAP3 pins as shown in Figure 25. The load capacitance at 3DCAP1, 3DCAP2 and 3DCAP3 pins should be 20pF(max), respectively. 3D1 bit 0 0 1 1 3D0 bit 0 1 0 1 3D Function 3D Effect Output Input Source OFF ON LOUT, ROUT Lineout summation circuit ON HPL, HPR Headphone summation circuit ON LOUT, ROUT, HPL, HPR Headphone summation circuit Table 25. 3D Function Power Management DP1 bit 0 0 1 1 DP0 bit 3D Depth 0 0% 1 50% 0 70% 1 100% Table 26. 3D depth setting Default Default 3DCAP1 pin 4.7nF 3DCAP2 pin 470nF 3DCAP3 pin Figure 25. 3D Function External Circuit MS0529-E-00 - 33 - 2006/07 ASAHI KASEI [AK4368EG] Power-Up/Down Sequence (EXT mode) 1) DAC HP-Amp Power Supply PDN pin (2) >0 PMVCM bit Don't care Clock Input (3) Don't care Don't care Don't care (1) >150ns (11) PMDAC bit DAC Internal State SDTI pin DACHL, DACHR bits 3D1-0 bits (when 3D is used) PMHPL, PMHPR bits MUTEN bit "00"(3D OFF) (4) >0 (5) >0 (4) >0 (5) >0 PD Normal Operation PD Normal Operation PD "10"(3D ON ) "00" "10" "00" (6) >2ms(at 3D OFF), >50ms(at 3D ON) (6) >2ms, or >50ms ATTL7-0 ATTR7-0 bits 00H(MUTE) FFH(0dB) (9) GD (10) 1061/fs (9) (10) 00H(MUTE) (7) FFH(0dB) (9) (10) 00H(MUTE) (9) (10) (8) (7) HPL/R pin (8) Figure 26. Power-up/down sequence of DAC and HP-amp (Don't care: except Hi-Z) (1) PDN pin should be set to "H" at least 150ns after power is supplied. (2) PMVCM and PMDAC bits should be changed to "1" after PDN pin goes "H". (3) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = "0", these clocks can be stopped. The headphone-amp can operate without these clocks. (4) DACHL and DACHR bits should be changed to "1" after the PMDAC bit is changed to "1". (5) When the 3D function is used, 3D1-0 bits should be changed to "10" after DACHL and DACHR bits are changed to "1". (6) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after the DACHL and DACHR bits are changed to "1". When the 3D function is used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "10". (7) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1F, tr = 70ms(typ). (8) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1F, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to "0" after HPL and HPR pins go to HVSS. After that, the DACL/DACR bits should be changed to "0" and 3D1-0 bits = "00". (9) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499s@fs=44.1kHz). (10) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (11) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become "L"). MS0529-E-00 - 34 - 2006/07 ASAHI KASEI 2) DAC Lineout Power Supply (1) >150ns PDN pin (2) >0 (6) Clock Input Don't care (5) >0 (at 3D OFF) PMDAC bit DAC Internal State SDTI pin DACL, DACR bits (3) >0 "01"(3D ON) (4) >0 "00" "01" PD(Power-down) (5) >0 (at 3D ON) Normal Operation PD Normal Operation Don't care [AK4368EG] PMVCM bit Don't care 3D1-0 bits "00"(3D OFF) (when 3D is used) PMLO bit ATTL/R7-0 bits 00H(MUTE) FFH(0dB) 00H(MUTE) FFH(0dB) LMUTE, ATTS3-0 bits 10H(MUTE) (8) GD (9) 1061/fs (8) (9) 0FH(0dB) (8) (7) (Hi-Z) (7) (9) LOUT/ROUT pins (Hi-Z) (7) Figure 27. Power-up/down sequence of DAC and LOUT/ROUT (Don't care: except Hi-Z) (1) (2) (3) (4) (5) PDN pin should be set to "H" at least 150ns after power is supplied. PMVCM bit should be changed to "1" after the PDN pin goes "H". DACL and DACR bits should be changed to "1" after the PMVCM bit is changed to "1". When the 3D function is used, 3D1-0 bits should be changed to "01" after DACL and DACR bits are changed to "1". When the 3D function is not used, the PMDAC and PMLO bits should be changed to "1" after the DACL and DACR bits are changed to "1". When the 3D function is used, the PMDAC and PMLO bits should be changed to "1" after 3D1-0 bits are changed to "01". External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = "0", these clocks can be stopped. The LOUT/ROUT buffer can operate without these clocks. When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499s@fs=44.1kHz). The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (6) (7) (8) (9) MS0529-E-00 - 35 - 2006/07 ASAHI KASEI 3) LIN/RIN/MIN HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit LINHL, MINHL, RINHR, MINHR bits Don't care [AK4368EG] (3) >0s 3D1-0 bits (when 3D is used) PMHPL/R bits "00" (3D OFF) (5) >0s "01", "10" or "11" (3D ON) "00" "01", "10" or "11" (6) >2ms or >50ms (6) >2ms(at 3D OFF), >50ms(at 3D ON) MUTEN bit (4) LIN/RIN/MIN pins (Hi-Z) (7) HPL/R pins (8) (7) (Hi-Z) Figure 28. Power-up/down sequence of LIN/RIN/MIN and HP-amp (1) PDN pin should be set to "H" at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to "1" after PDN pin goes "H". (3) LINHL, MINHL, RINHR and MINHR bits should be changed to "1" after PMVCM bit is changed to "1". (4) When LINHL, MINHL, RINHR or MINHR bit is changed to "1", LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) When the 3D function is used, 3D1-0 bits should be changed to "01", "10" or "11" after LINHL, MINHL, RINHR and MINHR bits are changed to "1". (6) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after LINHL, MINHL, RINHR and MINHR bits are changed to "1". When the 3D function is used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "01", "10" or "11". (7) Rise time of the headphone-amp is determined by an external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1F, tr = 70ms(typ). (8) Fall time of the headphone-amp is determined by an external capacitor (C) of MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1F, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to "0" after HPL and HPR pins go to HVSS. After that, LINHL, MINHL, RINHR and MINHR bits should be changed to "0". MS0529-E-00 - 36 - 2006/07 ASAHI KASEI 4) LIN/RIN/MIN Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don't care [AK4368EG] LINL, RINR, MINL, MINR bits (3) >0s 3D1-0 bits (when 3D is used) MUTEN bit "00" (3D OFF) (5) >0s "01", "10" or "11" (3D ON) "00" "01", "10" or "11" (6) >2ms or >50ms (6) >2ms(at 3D OFF), >50ms(at 3D ON) PMLO bit (4) LIN/RIN/MIN pins (Hi-Z) (Hi-Z) LMUTE, ATTS3-0 bits 10H(MUTE) 0FH(0dB) (7) (Hi-Z) LOUT/ROUT pins (Hi-Z) (7) (7) Figure 29. Power-up/down sequence of LIN/RIN/MIN and LOUT/ROUT (1) PDN pin should be set to "H" at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to "1" after PDN pin goes "H". (3) LINL, MINL, RINR and MINR bits should be changed to "1" after PMVCM bit is changed to "1". (4) When LINL, MINL, RINR or MINR bit is changed to "1", LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) When the 3D function is used, 3D1-0 bits should be changed to "01", "10" or "11" after LINL, MINL, RINR and MINR bits are changed to "1". (6) When the 3D function is not used, MUTEN and PMLO bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after LINL, MINL, RINR and MINR bits are changed to "1". When the 3D function is used, MUTEN and PMLO bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "01", "10" or "11". (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. MS0529-E-00 - 37 - 2006/07 ASAHI KASEI [AK4368EG] Power-Up/Down Sequence (PLL Slave mode) 1) DAC HP-Amp Power Supply PDN pin PMVCM, PMPLL, PMDAC, MCKO bits MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACHL, DACHR bits 3D1-0 bits (when 3D is used) PMHPL, PMHPR bits MUTEN bit Unstable (6) >0 (7) >0 (6) >0 (7) >0 PD Don't care Normal Operation Unstable PD Unstable Normal Operation PD Don't care (5) Unstable Don't care (4) ~20ms Unstable (4) ~20ms (2) >0 Don't care (3) Don't care (1) >150ns (13) Don't care Don't care "00"(3D OFF) "10"(3D ON ) "00" "10" "00" (8) >2ms(at 3D OFF), >50ms(at 3D ON) (8) >2ms, or >50ms ATTL7-0 ATTR7-0 bits 00H(MUTE) FFH(0dB) (11) GD (12) 1061/fs (11) (12) 00H(MUTE) (10) (9) (9) HPL/R pin FFH(0dB) 00H(MUTE) (11)(12) (11) (12) (10) Figure 30. Power-up/down sequence of DAC and HP-amp (Don't care: except Hi-Z) (1) (2) (3) (4) (5) (6) PDN pin should be set to "H" at least 150ns after power is supplied. PMVCM, PMPLL, PMDAC and MCKO bits should be changed to "1" after PDN pin goes "H". The PLL executes when the system clock is input to MCKI. The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. Table 1. After the PLL is locked, the MCKO pin outputs the master clock. The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = "0", these clocks can be stopped. The headphone-amp can operate without these clocks. (7) DACHL and DACHR bits should be changed to "1" after the PLL is locked. (8) When the 3D function is used, 3D1-0 bits should be changed to "10" after DACHL and DACHR bits are changed to "1". (9) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after the DACHL and DACHR bits are changed to "1". When the 3D function is used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "10". (10) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1F, tr = 70ms(typ). (11) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1F, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to "0" after HPL and HPR pins go to HVSS. After that, the DACL/DACR bits should be changed to "0" and 3D1-0 bits should be changed to "00". (12) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499s@fs=44.1kHz). (13) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (14) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become "L"). MS0529-E-00 - 38 - 2006/07 ASAHI KASEI 2) DAC Lineout Power Supply (1) >150ns PDN pin PMVCM, PMPLL, PMDAC, MCKO bits MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACL, DACR bits (6) >0 (7) >0 3D1-0 bits "00"(3D OFF) (when 3D is used) PMLO bit ATTL/R7-0 bits 00H(MUTE) "01"(3D ON) (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) 00H(MUTE) "00" (6) >0 (7) >0 "01" (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) PD Don't care Unstable Normal Operation Unstable PD Unstable Normal Operation Unstable (5) Unstable (4) ~20ms Unstable (4) ~20ms (2) >0 Don't care (3) Don't care [AK4368EG] Don't care LMUTE, ATTS3-0 bits 10H(MUTE) (10) GD (11) 1061/fs (10) (11) (Hi-Z) (9) 0FH(0dB) (10) (9) (Hi-Z) (9) (11) LOUT/ROUT pins Figure 31. Power-up/down sequence of DAC and LOUT/ROUT (Don't care: except Hi-Z) PDN pin should be set to "H" at least 150ns after power is supplied. PMVCM, PMPLL, PMDAC and MCKO bits should be changed to "1" after PDN pin goes "H". The PLL executes when the system clock is input to MCKI. The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. Table 1. After the PLL is locked, the MCKO pin outputs the master clock. The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = "0", these clocks can be stopped. The LOUT/ROUT buffer can operate without these clocks. (7) DACL and DACR bits should be changed to "1" after the PLL is locked (8) When the 3D function is used, 3D1-0 bits should be changed to "01" after DACL and DACR bits are changed to "1". (9) PMLO bit is changed to "1". (10) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (11) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499s@fs=44.1kHz). (12) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (1) (2) (3) (4) (5) (6) MS0529-E-00 - 39 - 2006/07 ASAHI KASEI 3) LIN/RIN/MIN HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit LINHL, MINHL, RINHR, MINHR bits Don't care [AK4368EG] (3) >0s 3D1-0 bits (when 3D is used) PMHPL/R bits "00" (3D OFF) (5) >0s "01", "10" or "11" (3D ON) "00" "01", "10" or "11" (6) >2ms or >50ms (6) >2ms(at 3D OFF), >50ms(at 3D ON) MUTEN bit (4) LIN/RIN/MIN pins (Hi-Z) (7) HPL/R pins (8) (7) (Hi-Z) Figure 32. Power-up/down sequence of LIN/RIN/MIN and HP-amp (1) PDN pin should be set to "H" at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to "1" after PDN pin goes "H". (3) LINHL, MINHL, RINHR and MINHR bits should be changed to "1" after PMVCM bit is changed to "1". (4) When LINHL, MINHL, RINHR or MINHR bit is changed to "1", LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) When the 3D function is used, 3D1-0 bits should be changed to "01", "10" or "11" after LINHL, MINHL, RINHR and MINHR bits are changed to "1".(refer to Table 25) (6) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after LINHL, MINHL, RINHR and MINHR bits are changed to "1". When the 3D function is used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "01", "10" or "11". (7) Rise time of the headphone-amp is determined by an external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1F, tr = 70ms(typ). (8) Fall time of the headphone-amp is determined by an external capacitor (C) of MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1F, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to "0" after HPL and HPR pins go to HVSS. After that, LINHL, MINHL, RINHR and MINHR bits should be changed to "0". MS0529-E-00 - 40 - 2006/07 ASAHI KASEI 4) LIN/RIN/MIN Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don't care [AK4368EG] LINL, RINR, MINL, MINR bits (3) >0s 3D1-0 bits (when 3D is used) MUTEN bit "00" (3D OFF) (5) >0s "01", "10" or "11" (3D ON) "00" "01", "10" or "11" (6) >2ms or >50ms (6) >2ms(at 3D OFF), >50ms(at 3D ON) PMLO bit (4) LIN/RIN/MIN pins (Hi-Z) (Hi-Z) LMUTE, ATTS3-0 bits 10H(MUTE) 0FH(0dB) (7) (Hi-Z) LOUT/ROUT pins (Hi-Z) (7) (7) Figure 33. Power-up/down sequence of LIN/RIN/MIN and LOUT/ROUT (1) PDN pin should be set to "H" at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to "1" after PDN pin goes "H". (3) LINL, MINL, RINR and MINR bits should be changed to "1" after PMVCM bit is changed to "1". (4) When LINL, MINL, RINR or MINR bit is changed to "1", LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) When the 3D function is used, 3D1-0 bits should be changed to "01", "10" or "11" after LINL, MINL, RINR and MINR bits are changed to "1".(refer to Table 25) (6) When the 3D function is not used, MUTEN and PMLO bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after LINL, MINL, RINR and MINR bits are changed to "1". When the 3D function is used, MUTEN and PMLO bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "01", "10" or "11". (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. MS0529-E-00 - 41 - 2006/07 ASAHI KASEI [AK4368EG] Power-Up/Down Sequence (PLL Master mode) 1) DAC HP-Amp Power Supply PDN pin (2) >0 M/S, PMVCM, PMPLL, PMDAC, MCKO bits Don't care (3) MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACHL, DACHR bits 3D1-0 bits (when 3D is used) PMHPL, PMHPR bits MUTEN bit Unstable (6) >0 (7) >0 (6) >0 (7) >0 PD Don't care Normal Operation Unstable PD Unstable Normal Operation PD Don't care "L" (5) Unstable Don't care (4) ~20ms Unstable (4) ~20ms Don't care (1) >150ns (13) Don't care Don't care "00"(3D OFF) "10"(3D ON ) "00" "10" "00" (8) >2ms(at 3D OFF), >50ms(at 3D ON) (8) >2ms, or >50ms ATTL7-0 ATTR7-0 bits 00H(MUTE) FFH(0dB) (11) GD (12) 1061/fs (11) (12) 00H(MUTE) (10) (9) (9) HPL/R pin FFH(0dB) 00H(MUTE) (11)(12) (11) (12) (10) Figure 34 Power-up/down sequence of DAC and HP-amp (Don't care: except Hi-Z) PDN pin should be set to "H" at least 150ns after power is supplied. PMVCM, PMPLL, PMDA, MCKO and M/S bits should be changed to "1" after PDN pin goes "H". The PLL executes when the system clock is input to MCKI. The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. Table 1. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins. DACHL and DACHR bits should be changed to "1" after the PLL is locked. When the 3D function is used, 3D1-0 bits should be changed to "10" after DACHL and DACHR bits are changed to "1". (8) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after the DACHL and DACHR bits are changed to "1". When the 3D function is used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "10". (9) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1F, tr = 70ms(typ). (10) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1F, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to "0" after HPL and HPR pins go to HVSS. After that, the DACL/DACR bits should be changed to "0" and 3D1-0 bits should be changed to "00". (11) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499s@fs=44.1kHz). (12) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (13) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become "L"). (1) (2) (3) (4) (5) (6) (7) MS0529-E-00 - 42 - 2006/07 ASAHI KASEI 2) DAC Lineout Power Supply (1) >150ns PDN pin M/S, PMVCM, PMPLL, PMDAC, MCKO bits MCKI pin Unstable MCKO pin Don't care BICK, LRCK pins Unstable DAC Internal State SDTI pin DACL, DACR bits (6) >0 (7) >0 3D1-0 bits "00"(3D OFF) (when 3D is used) PMLO bit ATTL/R7-0 bits 00H(MUTE) "01"(3D ON) (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) 00H(MUTE) "00" (6) >0 (7) >0 "01" (8) >0 (at 3D OFF) (8) >0 (at 3D ON) FFH(0dB) PD Don't care Unstable Normal Operation Unstable PD Unstable Normal Operation "L" (5) Unstable (4) ~20ms Unstable (4) ~20ms (2) >0 (3) Don't care [AK4368EG] Don't care Don't care LMUTE, ATTS3-0 bits 10H(MUTE) (10) GD (11) 1061/fs (10) (11) (Hi-Z) (9) 0FH(0dB) (10) (9) (Hi-Z) (9) (11) LOUT/ROUT pins Figure 35. Power-up/down sequence of DAC and LOUT/ROUT(Don't care: except Hi-Z) (1) PDN pin should be set to "H" at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to "1" after PDN pin goes "H". (3) The PLL executes when the system clock is input to MCKI. (4) The PLL lock time is referred to Note 26. Type 1-4 frequency is indicated in Table 2. (5) Table 1. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins. (6) DACL and DACR bits should be changed to "1" after the PLL is locked. (7) When the 3D function is used, 3D1-0 bits should be changed to "01" after DACL and DACR bits are changed to "1". (8) PMLO bit is changed to "1". (9) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (10) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499s@fs=44.1kHz). (11) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). MS0529-E-00 - 43 - 2006/07 ASAHI KASEI 3) LIN/RIN/MIN HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit LINHL, MINHL, RINHR, MINHR bits Don't care [AK4368EG] (3) >0s 3D1-0 bits (when 3D is used) PMHPL/R bits "00" (3D OFF) (5) >0s "01", "10" or "11" (3D ON) "00" "01", "10" or "11" (6) >2ms or >50ms (6) >2ms(at 3D OFF), >50ms(at 3D ON) MUTEN bit (4) LIN/RIN/MIN pins (Hi-Z) (7) HPL/R pins (8) (7) (Hi-Z) Figure 36. Power-up/down sequence of LIN/RIN/MIN and HP-amp (1) PDN pin should be set to "H" at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to "1" after PDN pin goes "H". (3) LINHL, MINHL, RINHR and MINHR bits should be changed to "1" after PMVCM bit is changed to "1". (4) When LINHL, MINHL, RINHR or MINHR bit is changed to "1", LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) When the 3D function is used, 3D1-0 bits should be changed to "01", "10" or "11" after LINHL, MINHL, RINHR and MINHR bits are changed to "1".(refer to Table 25) (6) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after LINHL, MINHL, RINHR and MINHR bits are changed to "1". When the 3D function is used, PMHPL, PMHPR and MUTEN bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "01", "10" or "11". (7) Rise time of the headphone-amp is determined by an external capacitor (C) of MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1F, tr = 70ms(typ). (8) Fall time of the headphone-amp is determined by an external capacitor (C) of MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1F, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to "0" after HPL and HPR pins go to HVSS. After that, LINHL, MINHL, RINHR and MINHR bits should be changed to "0". MS0529-E-00 - 44 - 2006/07 ASAHI KASEI 4) LIN/RIN/MIN Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don't care [AK4368EG] LINL, RINR, MINL, MINR bits (3) >0s 3D1-0 bits (when 3D is used) MUTEN bit "00" (3D OFF) (5) >0s "01", "10" or "11" (3D ON) "00" "01", "10" or "11" (6) >2ms or >50ms (6) >2ms(at 3D OFF), >50ms(at 3D ON) PMLO bit (4) LIN/RIN/MIN pins (Hi-Z) (Hi-Z) LMUTE, ATTS3-0 bits 10H(MUTE) 0FH(0dB) (7) (Hi-Z) LOUT/ROUT pins (Hi-Z) (7) (7) Figure 37. Power-up/down sequence of LIN/RIN/MIN and LOUT/ROUT (1) PDN pin should be set to "H" at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to "1" after PDN pin goes "H". (3) LINL, MINL, RINR and MINR bits should be changed to "1" after PMVCM bit is changed to "1". (4) When LINL, MINL, RINR or MINR bit is changed to "1", LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) When the 3D function is used, 3D1-0 bits should be changed to "01", "10" or "11" after LINL, MINL, RINR and MINR bits are changed to "1".(refer to Table 25) (6) When the 3D function is not used, MUTEN and PMLO bits should be changed to "1" at least 2ms (in case external capacitance at VCOM pin is 2.2F) after LINL, MINL, RINR and MINR bits are changed to "1". When the 3D function is used, MUTEN and PMLO bits should be changed to "1" at least 50ms after 3D1-0 bits are changed to "01", "10" or "11". (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. MS0529-E-00 - 45 - 2006/07 ASAHI KASEI [AK4368EG] Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = "L") Internal registers may be written to via the 3-wire P interface pins (CSN, CCLK and CDTI). The data on this interface consists of the Chip address (2-bits, Fixed to "01"), Read/Write (1-bit, Fixed to "1", Write only), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). Address and data are clocked in on the rising edge of CCLK. For write operations, the data is latched after a low-to-high transition of the 16th CCLK. The clock speed of CCLK is 5MHz(max). The value of the internal registers is initialized at PDN pin = "L". CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to "01") READ/WRITE (Fixed to "1", Write only) Register Address Control Data Figure 38. 3-wire Serial Control I/F Timing MS0529-E-00 - 46 - 2006/07 ASAHI KASEI [AK4368EG] (2) I2C-bus Control Mode (I2C pin = "H") The AK4368 supports fast-mode I2C-bus (max: 400kHz, Version 1.0). (2)-1. WRITE Operations Figure 39 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 45). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as "001000". The next bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets this device address bit (Figure 40). If the slave address matches that of the AK4368, the AK4368 generates an acknowledgement and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 46). A R/W bit value of "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4368. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 41). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 42). The AK4368 generates an acknowledgement after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 45). The AK4368 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4368 generates an acknowledgement and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0CH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 47) except for the START and STOP conditions. S T A R T R/W="0" S T O P Sub Address(n) Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P SDA Slave S Address A C K Figure 39. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 0 CAD0 R/W (Those CAD0 should match with CAD0 pin) Figure 40. The First Byte 0 0 0 A4 A3 A2 A1 A0 Figure 41. The Second Byte D7 D6 D5 D4 D3 D2 D1 D0 Figure 42. Byte Structure after the second byte MS0529-E-00 - 47 - 2006/07 ASAHI KASEI [AK4368EG] (2)-2. READ Operations Set the R/W bit = "1" for the READ operation of the AK4368. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0CH prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4368 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4368 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4368 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledgement to the data but instead generates a stop condition, the AK4368 ceases transmission. S T A R T R/W="1" S T O P Data(n) Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P SDA Slave S Address A C K Figure 43. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start request, a slave address (R/W bit = "0") and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to "1". The AK4368 then generates an acknowledgement, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledgement to the data but instead generates a stop condition, the AK4368 ceases transmission. S T A R T S T A R T Sub Address(n) A C K A C K R/W="0" R/W="1" S T O P Data(n) Data(n+1) A C K A C K A C K Data(n+x) A C K P SDA Slave S Address Slave S Address A C K Figure 44. RANDOM ADDRESS READ MS0529-E-00 - 48 - 2006/07 ASAHI KASEI [AK4368EG] SDA SCL S start condition P stop condition Figure 45. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement 1 2 8 9 START CONDITION Figure 46. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 47. Bit Transfer on the I2C-Bus MS0529-E-00 - 49 - 2006/07 ASAHI KASEI [AK4368EG] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH Register Name Power Management PLL Control Clock Control Mode Control 0 Mode Control 1 DAC Lch ATT DAC Rch ATT Headphone Out Select Lineout Select Lineout ATT ALC Mode Control 1 ALC Mode Control 2 3D Control D7 0 FS3 0 0 ATS ATTL7 ATTR7 0 0 0 REF7 0 0 D6 PMPLL FS2 0 MONO1 DATTC D5 PMLO FS1 M/S MONO0 LMUTE D4 MUTEN D3 PMHPR D2 PMHPL PLL2 D1 PMDAC D0 PMVCM FS0 MCKAC BCKP SMUTE ATTL6 ATTR6 HPG LOG 0 REF6 0 0 ATTL5 ATTR5 MINHR MINR ATTL4 ATTR4 MINHL MINL PLL3 BF LRP BST1 ATTL3 ATTR3 RINHR RINR ATTS3 PS0 DIF2 BST0 ATTL2 ATTR2 LINHL LINL ATTS2 PLL1 PS1 DIF1 DEM1 ATTL1 ATTR1 DACHR DACR ATTS1 PLL0 MCKO DIF0 DEM0 ATTL0 ATTR0 DACHL DACL ATTS0 0 REF5 ALC 0 0 REF4 ROTM1 0 REF3 ROTM0 DP1 REF2 LMAT1 DP0 REF1 LMAT0 3D1 REF0 RATT 3D0 All registers inhibit writing at PDN pin = "L". PDN pin = "L" resets the registers to their default values. For addresses from 0DH to 1FH, data must not be written. Unused bits must contain a "0" value. MS0529-E-00 - 50 - 2006/07 ASAHI KASEI [AK4368EG] Register Definitions Addr 00H Register Name Power Management R/W Default D7 0 RD 0 D6 PMPLL R/W 0 D5 PMLO R/W 0 D4 MUTEN D3 PMHPR D2 PMHPL D1 PMDAC D0 PMVCM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PMVCM: Power Management for VCOM Block 0: Power OFF (Default) 1: Power ON PMDAC: Power Management for DAC Blocks 0: Power OFF (Default) 1: Power ON When the PMDAC bit is changed from "0" to "1", the DAC is powered-up to the current register values (ATT value, sampling rate, etc). PMHPL: Power Management for the left channel of the headphone-amp 0: Power OFF (Default). HPL pin goes to HVSS(0V). 1: Power ON PMHPR: Power Management for the right channel of the headphone-amp 0: Power OFF (Default). HPR pin goes to HVSS(0V). 1: Power ON MUTEN: Headphone Amp Mute Control 0: Mute (Default). HPL and HPR pins go to HVSS(0V). 1: Normal operation. HPL and HPR pins go to 0.475 x AVDD. PMLO: Power Management for Stereo Output 0: Power OFF (Default) LOUT/ROUT pins go to Hi-Z. 1: Power ON PMPLL: Power Management for PLL 0: Power OFF: EXT mode (Default) 1: Power ON: PLL mode Each block can be powered-down respectively by writing "0" in each bit of this address. When the PDN pin is "L", all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value. When PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMPLL and MCKO bits are "0", all blocks are powered-down. The register values remain unchanged. Power supply current is 20A(typ) in this case. For fully shut down (typ. 1A), PDN pin should be "L". Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 PLL2 01H PLL Control FS3 FS2 FS1 FS0 PLL3 PLL1 PLL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 0 0 0 0 FS3-0: Select Sampling Frequency PLL mode: Table 2 EXT mode: Table 6 PLL3-0: Select MCKI Frequency PLL mode: Note 26. Type 1-4 frequency is indicated in Table 2. Table 1 EXT mode: Disable MS0529-E-00 - 51 - 2006/07 ASAHI KASEI [AK4368EG] Addr 02H Register Name Clock Control R/W Default D7 0 RD 0 D6 0 RD 0 D5 M/S R/W 0 D4 MCKAC R/W 0 D3 BF R/W 0 D2 PS0 R/W 0 D1 PS1 R/W 0 D0 MCKO R/W 0 MCKO: Control of MCKO signal 0: Disable (Default) 1: Enable PS1-0: MCKO Frequency PLL mode: Table 3 EXT mode: Table 7 BF: BICK Period setting in Master Mode. In slave mode, this bit is ignored. 0: 32fs (Default) 1: 64fs MCKAC: MCKI Input Mode Select 0: CMOS input (Default) 1: AC coupling input M/S: Master/Slave Mode Select 0: Slave mode (Default) 1: Master mode Addr 03H Register Name Mode Control 0 R/W Default D7 0 RD 0 D6 MONO1 D5 MONO0 R/W 0 R/W 0 D4 BCKP R/W 0 D3 LRP R/W 0 D2 DIF2 R/W 0 D1 DIF1 R/W 1 D0 DIF0 R/W 0 DIF2-0: Audio Data Interface Format Select (Table 11) Default: "010" (Mode 2) LRP: LRCK Polarity Select in Slave Mode 0: Normal (Default) 1: Invert BCKP: BICK Polarity Select in Slave Mode 0: Normal (Default) 1: Invert MONO1-0: Mixing Select (Table 21) Default: "00" (LR) MS0529-E-00 - 52 - 2006/07 ASAHI KASEI [AK4368EG] Addr 04H Register Name Mode Control 1 R/W Default D7 ATS R/W 0 D6 DATTC D5 LMUTE D4 SMUTE R/W 0 R/W 1 R/W 0 D3 BST1 R/W 0 D2 BST0 R/W 0 D1 DEM1 R/W 0 D0 DEM0 R/W 1 DEM1-0: De-emphasis Filter Frequency Select (Table 19) Default: "01" (OFF) BST1-0: Low Frequency Boost Function Select (Table 20) Default: "00" (OFF) SMUTE: Soft Mute Control 0: Normal operation (Default) 1: DAC outputs soft-muted LMUTE: Mute control for LOUT/ROUT (Table 24) 0: Normal operation. ATTS3-0 bits control attenuation value. 1: Mute. ATTS3-0 bits are ignored. (Default) DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (Default) 1: Dependent At DATTC bit = "1", ATTL7-0 bits control both channel attenuation levels, while register values of ATTL7-0 bits are not written to the ATTR7-0 bits. At DATTC bit = "0", the ATTL7-0 bits control the left channel level and the ATTR7-0 bits control the right channel level. ATS: Digital attenuator transition time setting (Table 18) 0: 1061/fs (Default) 1: 7424/fs Addr 05H 06H Register Name DAC Lch ATT DAC Rch ATT R/W Default D7 ATTL7 ATTR7 R/W 0 D6 ATTL6 ATTR6 R/W 0 D5 ATTL5 ATTR5 R/W 0 D4 ATTL4 ATTR4 R/W 0 D3 ATTL3 ATTR3 R/W 0 D2 ATTL2 ATTR2 R/W 0 D1 ATTL1 ATTR1 R/W 0 D0 ATTL0 ATTR0 R/W 0 ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 17) ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 17) Default: "00H" (MUTE) MS0529-E-00 - 53 - 2006/07 ASAHI KASEI [AK4368EG] Addr 07H Register Name Headphone Out Select R/W Default D7 0 RD 0 D6 HPG R/W 0 D5 MINHR D4 MINHL D3 RINHR D2 LINHL D1 DACHR D0 DACHL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DACHL: DAC left channel output signal is added to the left channel of the headphone-amp. 0: OFF (Default) 1: ON DACHR: DAC right channel output signal is added to the right channel of the headphone-amp. 0: OFF (Default) 1: ON LINHL: Input signal to LIN pin is added to the left channel of the headphone-amp. 0: OFF (Default) 1: ON RINHR: Input signal to RIN pin is added to the right channel of the headphone-amp. 0: OFF (Default) 1: ON MINHL: Input signal to MIN pin is added to the left channel of the headphone-amp. 0: OFF (Default) 1: ON MINHR: Input signal to MIN pin is added to the right channel of the headphone-amp. 0: OFF (Default) 1: ON HPG: DAC HPL/R Gain 0: 0.76dB (Default) 1: +6.76dB MS0529-E-00 - 54 - 2006/07 ASAHI KASEI [AK4368EG] Addr 08H Register Name Lineout Select R/W Default D7 0 RD 0 D6 LOG R/W 0 D5 MINR D4 MINL D3 RINR D2 LINL D1 DACR D0 DACL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DACL: DAC left channel output is added to the LOUT buffer amp. 0: OFF (Default) 1: ON DACR: DAC right channel output is added to the ROUT buffer amp. 0: OFF (Default) 1: ON LINL: Input signal to the LIN pin is added to the LOUT buffer amp. 0: OFF (Default) 1: ON RINR: Input signal to the RIN pin is added to the ROUT buffer amp. 0: OFF (Default) 1: ON MINL: Input signal to the MIN pin is added to the LOUT buffer amp. 0: OFF (Default) 1: ON MINR: Input signal to the MIN pin is added to the ROUT buffer amp. 0: OFF (Default) 1: ON LOG: DAC LOUT/ROUT Gain 0: 0dB (Default) 1: +6dB Addr 09H Register Name Lineout ATT R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 D3 ATTS3 D2 ATTS2 D1 ATTS1 D0 ATTS0 R/W 0 R/W 0 R/W 0 R/W 0 ATTS3-0: Analog volume control for LOUT/ROUT (Table 24) Default: LMUTE bit = "1", ATTS3-0 bits = "0000" (MUTE) Setting of ATTS3-0 bits is enabled at LMUTE bit is "0". MS0529-E-00 - 55 - 2006/07 ASAHI KASEI [AK4368EG] Addr 0AH Register Name ALC Mode Control 1 R/W Default D7 REF7 R/W 1 D6 REF6 R/W 0 D5 REF5 R/W 0 D4 REF4 R/W 1 D3 REF3 R/W 0 D2 REF2 R/W 0 D1 REF1 R/W 0 D0 REF0 R/W 1 REF7-0: Reference Value for ALC Recovery Operation, 0.375dB step, 81 level, Default: "91H" (Table 15) Addr 0BH Register Name ALC Mode Control 2 R/W Default D7 0 RD 0 D6 0 RD 0 D5 ALC R/W 0 D4 ROTM1 D3 ROTM0 D2 LMAT1 D1 LMAT0 D0 RATT R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 RATT: ALC Recovery GAIN Step (Table 14) LMAT1-0: ALC Limiter ATT Step (Table 13) ROTM1-0: ALC Recovery Waiting Period, Limiter/Recovery Operation Zero Crossing Timeout Period (Table 12) ALC: ALC Enable 0: ALC Disable (Default) 1: ALC Enable Addr 0CH Register Name 3D Control R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 D3 DP1 D2 DP0 D1 3D1 D0 3D0 RD 0 R/W 0 R/W 0 R/W 0 R/W 0 3D1-0: 3D Stereo Enhancement Enable (Table 25) Default: "00" (Disable) DP1-0: 3D Depth (Table 26) Default: "00" (0%) MS0529-E-00 - 56 - 2006/07 ASAHI KASEI [AK4368EG] SYSTEM DESIGN Figure 48 shows the system connection diagram. An evaluation board [AKD4368] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Analog Supply 1.63.6V 220 + + 220 16 16 NC HPR HVSS HVDD AVDD VCOM LOUT NC + 10 0.1 2.2 0.1 1 Speaker SPK-Amp Headphone HPL AVSS MUTET ROUT 3DCAP2 3DCAP3 470n 4.7n MIN NC NC 3DCAP1 RIN NC Top View NC PDN NC Cp Rp 0.1 10 VCOC LIN NC CAD0/ CSN SCL/ CCLK NC PVDD NC PVSS MCKO DVSS DVDD I2C MCKI LRCK BICK SDATA SDA/ CDTI 0.1 1000p Audio Controller P Notes: - AVSS, DVSS, HVSS and PVSS of the AK4368 should be distributed separately from the ground of external controllers. - Do not let digital input pins float. - When the AK4368 is in EXT mode (PMPLL bit = "0"), a resistor and capacitor for the VCOC pin is not needed. - When the AK4368 is in PLL mode (PMPLL bit = "1"), a resistor and capacitor for the VCOC pin is shown in Note 26. Type 1-4 frequency is indicated in Table 2. Table 1. - When the AK4368 is used in master mode, LRCK and BICK pins are floating before the M/S bit is changed to "1". Therefore, a 100k pull-up resistor should be connected to the LRCK and BICK pins of the AK4368. Figure 48. Typical Connection Diagram (In case of AC coupling to MCKI) MS0529-E-00 - 57 - 2006/07 ASAHI KASEI [AK4368EG] 1. Grounding and Power Supply Decoupling The AK4368 requires careful attention to power supply and grounding arrangements. AVDD, PVDD and HVDD are usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10 resistor. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. When AVDD and HVDD are supplied separately, AVDD is powered-up at the same time or earlier than HVDD. When the AK4368 is powered-down, HVDD is powered-down at the same time or later than AVDD. The power up sequence of PVDD is not critical. AVSS, DVSS, PVSS and HVSS must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4368 as possible, with the small value ceramic capacitors being the nearest. 2. Voltage Reference The input voltage to AVDD sets the analog output range. A 0.1F ceramic capacitor and a 10F electrolytic capacitor are connected between AVDD and AVSS. VCOM is a signal ground of this chip (0.475 x AVDD). An electrolytic 2.2F attached between VCOM and AVSS eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from AVDD and VCOM in order to avoid unwanted coupling into the AK4368. 3. Analog Outputs The analog outputs are single-ended outputs, and 0.47 x AVDD Vpp(typ)@-3dBFS for headphone-amp and 0.61xAVDD Vpp(typ) @0dBFS for LOUT/ROUT centered on the VCOM voltage. The input data format is 2's compliment. The output voltage is a positive full scale for 7FFFFFH(@24bit) and negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM plus a few mV. MS0529-E-00 - 58 - 2006/07 ASAHI KASEI [AK4368EG] PACKAGE 4.0 0.1 41 - 0.3 0.05 0.15 M S AB 7 6 5 4 3 2 1 A B A B 4.0 0.1 C 3.0 D E F G 0.5 3.0 0.5 S Package & Lead frame material Package molding compound: Epoxy Interposer material: BT resin Solder ball material: SnAgCu MS0529-E-00 - 59 - 0.23 0.05 0.08 S 1.0MAX 2006/07 ASAHI KASEI [AK4368EG] MARKING 4368 XXXX XXXX: Date code (4 digit) Pin #1 indication Revision History Date (YY/MM/DD) 06/07/25 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0529-E-00 - 60 - 2006/07 |
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